Abstract
A double quasi-cyclic low density parity check (DQC-LDPC) code and a corresponding processor is disclosed herein. The parity check matrix of DQC-LDPC codes has regularity with its corresponding processor including an input end, an output end and a processing module. The parity-check matrix includes a double quasi-cyclic matrix. The double quasi-cyclic matrix includes a plurality of sub-matrices. The sub-matrices are arranged in an array. Each sub-matrix includes a plurality of entries, and each sub-matrix is a circulant matrix with corresponding entries been circulants. The double quasi-cyclic matrix is a circulant matrix of circulants. The processing module is configured to process an input signal and output an output signal correspond to a parity-check matrix of a low density parity check code(LDPC).