Abstract
The present invention discloses a static random access memory cell, which comprises the first inverter, the second inverter, the first transistor, the second transistor, and the third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and the first output node of the first inverter. Moreover, the second transistor is connected with a complementary write bit line, the write word line, and the second output node of the second inverter, so as to respectively form a pass gate. Furthermore, the third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter, so as to form a read port transistor. Thereby, the memory cell has a read port. Wherein, the read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line, and the read bit line swing can be expanded through a boosted read bit line.