Abstract
A non-volatile memory having isolation structure, floating gate transistor, a specific dielectric layer and an erase gate is provided. The isolation structure is disposed in the substrate to define an active region. The floating gate transistor having a floating gate, a tunneling dielectric layer, a first source/drain region and a second source/drain region is disposed on the substrate. The floating gate is disposed on the substrate and across to the active region. The tunneling dielectric layer is disposed between the floating gate and the substrate. The first source/drain region and the second source/drain region are disposed in the substrate at the sides of the floating gate respectively. The specific dielectric layer is served as an inter-gate dielectric layer which is disposed on top of floating gate. The erase gate is a conductive plug disposed on the specific dielectric layer.