Abstract
A method allows that the instructions of a PAC processor undergo software pipelining schedule while compiling. In order to avoid inferior scheduling results due to the ping-pong constraint of global register files, the virtual register files are allocated to local register files as far as possible, then the number of required periods of loops undergoing pipelining schedule for each iteration is calculated. Modulo scheduling algorithm is performed and the instructions of the loops are assigned to the fixed period, thereby allocating the registers. If excess virtual registers are allocated to the local register files that induces the register allocation fails, a transparent register transformation mechanism re-allocates the virtual register originally assigned to the local register files to the global register files, so as to increase the successful rates of register allocation and the software pipelining schedule.